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CSEB332: Digital Design with HDL Lab

Description:Experiments and projects utilizing the hardware description language, EDA software tools, soft-core processor and FPGA devices to design, synthesize, simulate, implement and test digital systems.
Credit Hours.:1
Text Book: Digital hardware Design Lab Manual
Coordinator: Fekri Kharbash
Topics Outline:
  1. Introduction to the lab design environment
  2. Verilog primitive operators and structural Verilog
  3. Structural Modeling
  4. Hierarchical Modeling
  5. Behavioral Modeling
  6. Combinational circuits
  7. Sequential circuits
  8. State machines
  9. Arithmetic-Logic Unit Modeling
  10. Hardware design of a simple computer
Outcomes:
  1. Demonstrate hands-on knowledge in applying concepts and methods of digital system design techniques with HDL
  2. Follow HDL Coding Standards used in the industry and employ industry standard EDA tools to design, implement and test digital systems on FPGAs
  3. Analyze the results of logic and timing simulations and to use these simulation results to debug digital systems
  4. Understand and use of modern EDA tools for FPGA design
  5. Design a stand-alone application
Mapping of Topics Outline to Outcomes
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Pre-requisite
Co-requisite CSEB310: Digital Design With HDL
Volume of the Course that Contributes to CIT Students Outcomes(SOs)
Move the mouse over the Students Outcome number to view the Students Outcome text
a b c d e f g h i j k l m n
15% 13% 22% 13% 0% 6%0% 0% 20% 8% 11% 2% 8% 2%
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