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CSEB310: Digital Design With HDL

Description:Introduction to digital design with a hardware description language; Field Programmable Gate Arrays and complex programmable logic devices; Finite state machine design; CAD tools for field programmable gate arrays and programmable array logic; Parallel and serial input/output techniques; Behavioral, schematic, and net list description of digital systems. (Prerequisite: ITBP205).
Credit Hours.:3
Text Book: Michael D. Ciletti, Advanced Digital Design with the Verilog HDL. Prentice Hall
Coordinator: Fekri Kharbash
Topics Outline:
  1. Defining steps of digital design methodology and designing combinational logic circuits using the traditional method - Overview
  2. Distinguishing between function and logic hazards and eliminating logic hazards from digital circuits
  3. Designing combinational logic circuits using the HDL and using an HDL simulator to verify the correctness of HDL codes
  4. Designing sequential logic circuits using the traditional method - Overview and using HDL
  5. Creating testbenches
  6. Performing state minimization to reduce the number of states in a finite state machine
  7. Modeling datapath circuits using HDL
  8. Using a synthesis tool to synthesize HDL codes
  9. Identifying and evaluating the different types of programmable logic devices
  10. Serial and parallel I/O techniques
  1. Describe the digital design methodologies and various types of programmable logic devices.
  2. Design logic circuits and finite state machines using traditional and HDL methods.
  3. Distinguish between function and logic hazards.
  4. Eliminate logic hazards from digital circuits.
  5. Apply state minimization techniques to finite state machines.
  6. Use an HDL simulator and synthesis tool with the FPGA to compile, simulate and synthesize digital systems.
Mapping of Topics Outline to Outcomes
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Pre-requisiteCSEB301: Circuits Fundamentals
ITBP205: Digital Design and Computer Organization
Co-requisite CSEB332: Digital Design with HDL Lab
Volume of the Course that Contributes to CIT Students Outcomes(SOs)
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