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CSEB321: Hardware Testing and Fault Tolerance

Description:Faults and fault models, Reliability, Availability, MTTF, MTBF; Reliability block diagrams; Redundancy techniques; Error detection and correction in memory, buses, networks, and execution units; Testing of digital and combinational circuits; builtin self test (BIST), scan techniques and JTAG; RAS techniques in modern computer systems. (Prerequisite: CSEB300 and CSEB310).
Credit Hours.:3
Text Book: Fault-Tolerant Design E. Dubrova Springer ISBN 978-1-4614-2113-9
Coordinator: Valeriu Beiu
Topics Outline:
  1. VLSI Life Cycle Testing
  2. Challenges in VLSI Testing
  3. Levels of Abstraction in VLSI Testing
  4. Design for Testability
  5. Logic and Fault Simulation
  6. Test Generation
  7. Built-in Self-Test (BIST)
  8. Memory Testing
  9. Trends in the Nanometer Age
  1. Define Reliability, Availability, MTTF, and MTBF.
  2. Apply testing techniques to modern computer systems and circuits.
  3. Derive the reliability block diagram of hardware systems.
  4. Apply error detection, correction, and redundancy techniques in the design of fault-tolerant hardware.
  5. Explain the operation of JTAG, scan, and BIST techniques.
Mapping of Topics Outline to Outcomes
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Pre-requisiteCSEB300: Computer Architecture
CSEB310: Digital Design With HDL
Volume of the Course that Contributes to CIT Students Outcomes(SOs)
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a b c d e f g h i j k l m n
9% 11% 11% 0% 0% 0%7% 4% 16% 7% 16% 7% 7% 0%
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